Thermal print head wafer and method of making the same

ABSTRACT

A thermal print head wafer including a dielectric substrate having one end whose sharp edges are removed (by grinding) to provide a continuous, blended surface between an intended printing surface of the substrate and opposed flat sides thereof. The blended surface has small grooves in the surface thereof, which grooves are aligned parallel to a direction in which the print wafer moves relative to a thermally responsive record medium with which the printing wafer is used. A layer of semiconductor material is deposited (by pulse spraying) on the blended surface while a portion of the substrate is heated in a furnace, and the deposited material is separated into discrete, spaced resistive elements by high-pressure spraying of abrasives at the semiconductor material through a slitted U-shaped mask. Electrical conductors (located on the opposed flat sides) of the substrate are connected to the ends of the resistive elements, enabling them to be selectively energized.

United States Patent [72] Inventor William L. Colello Troy, Ohio [21] Appl. No. 869,700

[22] Filed Oct. 27, 1969 {45] Patented May 18,197]

{73] Assignee The National Cash Register Company Dayton, Ohio [54] THERMAL PRINT HEAD WAFER AND METHOD Primary Examiner-J. V. Truhe Assistant ExaminerC. L. Albritton Attorneys-Louis A. Kline, Albert L. Sessler, Jr. and Elmer Wargo ABSTRACT: A thermal print head wafer including a dielectric substrate having one end whose sharp edges are removed (by grinding) to provide a continuous, blended surface between an intended printing surface of the substrate and opposed flat sides thereof. The blended surface has small grooves in the surface thereof, which grooves are aligned parallel to a direction in which the print wafer moves relative to a thermally responsive record medium with which the printing wafer is used. A layer of semiconductor material is deposited (by pulse spraying) on the blended surface while a portion of the substrate is heated in a furnace, and the deposited material is separated into discrete, spaced resistive elements by high-pressure spraying of abrasives at the semiconductor material through a slitted Ushaped mask. Electrical conductors (located on the opposed flat sides) of the substrate are connected to the ends of the resistive elements, enabling them to be selectively energized.

" Patented May 18, 1971 3,578,946

2 Sheets-Sheet 1 NTO WILL L. C LLO H S ATTORNEYS THERMAL PRINT HEAD WAFER AND METHOD OF MAKING THE SAME BACKGROUND OF THE INVENTION This invention relates to a thermal print head wafer and the method of making it.

The print head wafer of this invention is capable of making a mark on a thermally sensitive record medium. The wafer is composed of a substrate member made of high-resistivity material upon at least one surface of which are selectively positioned a plurality of small resistive elements having respective individual electrically-conductive circuits connected thereto. A short-duration electrical pulse passing through any one of the circuits produces in the corresponding resistive element a temperature rise of sufficient magnitude to produce a mark on a thermally sensitive record medium used in cooperative association therewith.

Efforts are continually being made to improve the reliability and the stability of the print head wafers and to reduce the cost of manufacturing them. Two print head wafers of the prior art are shown in US. Pat. No. 3,161,457, issued Dec. [5, 1964, on the application of Hans Schroeder et al., and US. Pat. No. 3,340,381, issued Sept. 5, 1967, on the application of Gary R. Best.

The present invention improves the reliability of the print head wafers, reduces the cost of manufacturing them, and also improves the appearance of the marks produced thereby. For example, because the substrate material near the resistive elements is not removed during the process of forming individual resistive elements in this invention, the substrate has an increased heat-sinking capability, which increases the useful life of the resistive elements when compared to some prior-art print wafers whose individual resistive elements are formed by slitting with a diamond saw. The present invention uses an abrasion-cutting technique instead of slitting with a saw to form the individual resistive elements, and, consequently, the widths of the resistive elements are increased and the spacing between them is decreased. The wider resistive element provides for an increased power rating thereof,'and the decreased spacing between adjacent elements provides for an improved appearance of the characters formed thereby when several print head wafers are formed into a print head matrix. These advantages and others will become more readily understood upon reading the detailed description of the invention.

SUMMARY OF THE INVENTION This invention relates to a thermal print head wafer and the method of making it.

The print head wafer is composed of a dielectric substrate having first and second opposed planar surfaces which are mutually substantially perpendicular to a third surface thereof. The first, second, and third surfaces are machined to provide one continuous blended area extending completely over the third surface and partly over the first and second surfaces. The blended area has small grooves therein below the surface thereof, and the grooves are aligned substantially parallel to an imaginary plane perpendicular to said first, second, and third surfaces. A layer of semiconductor material from which the resistive elements of the wafer are formed is deposited on the blended area by spraying. During the sprayingoperation, the blended area of the substrate is located outside a furnace, while the remaining portion of the substrate is heated within the furnace. After the semiconductor layer is deposited on the blended area, the layer is separated into discrete resistor elements by spraying abrasive material through a slitted mask at the semiconductor layer. Electrical conductors contacting the ends of the resistive elements enable them to be selectively energized. Several such print head wafers, assembled together with insulators between adjacent wafers, form a print head matrix.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view of a portion of a substrate on which a plurality of resistive elements will be formed.

FIG. 2 is a perspective view of the substrate shown in FIG. 1 after the substrate is machined to provide one continuous blended area upon which the resistive elements will be formed.

FIG. 3 is a perspective view of the substrate as received from FIG. 2, showing the step of applying a semiconductor material over selected sides of the substrate, including the blended area.

FIG. 4 is a perspective view of the substrate as received from FIG. 3 with the semiconductor material deposited thereon and trimmed as shown.

FIG. 5 is a perspective view of the substrate with the trimmed layer of semiconductor material thereon being divided into discrete resistive elements.

FIG. 6 is a perspective view of a portion of the substrate of FIG. 5 showing the discrete resistive elements formed from the dividing step shown in FIG. 5.

FIG. 7 is a perspective view of the substrate and resistive elements shown in FIG. 6 after electrical conductors are attached to each of said elements.

FIG. 8 is a perspective view of two completed substrates with resistive elements and conductors thereon forming separate print wafers which are separated by a dielectric member.

FIG. 9 is a perspective view of a completed matrix-type, thermal-print head made up of several print head wafers separated by dielectric members, which print head wafers are made according to the steps shown in FIGS. 1 to 8 inclusive.

FIG. 10 is a front elevational view of a special grinding apparatus which is used to form the blended area on the substrate. 5

FIG. 11 is a side elevational view of the grinding apparatus of FIG. 10, showing more details thereof.

DETAILED DESCRIPTION It appears as though the details of the thermal print wafer of this invention, designated generally as 20 in FIG. 8, can best be described in conjunction with a description of the method of producing the wafer. Accordingly, the method as portrayed in FIGS. 1 to 7, inclusive, will be described in detail.

FIG. 1 shows a perspective view of a portion of a dielectric substrate, designated generally as 22, on which a plurality of resistive elements (not shown) will be formed. The size of the substrate is dependent upon particular design requirements; however, to illustrate the invention, one embodiment thereof was approximately 1.000 inch wide, 1.562 inches long, and 0.018 inch thick. The substrate 22 has first and second opposed, parallel surfaces 24 and 26, respectively, which are mutually, substantially perpendicular to a third surface 28 lying therebetween. The first and third surfaces 24 and 28 join in a first common edge 30, and, similarly, the second and third surfaces 26 and 28 join in a second common edge .32. The substrate 22 is formed of dielectric materials like glass, porcelain, or ceramics. The dielectric material selected should have a coefficient of expansion close to that of the semiconductor material from which the resistive elements will be formed, so as to minimize changes in expansion therebetween.

The substrate 22 shown in FIG. 1 is then machined to produce a continuous blended area, designated generally as 34 and shown in FIG. 2. A special grinding apparatus (to be later described in connection with FIGS. 10 and 11) is used to form the blended area 34. The blended area 34 is formed by grinding an accurate radius at 38 (FIGIZ) to remove the first common edge 30 and by grinding an identical accurate radius at 40 to remove the second common edge 32 in addition to grinding the third surface 28 therebetween. In the embodiment shown, the radii at 38 and 40 are 0.003 inch. The grinding operation is so performed that the grinding marks or grooves resulting therefrom will be parallel tothe flow of electrical energy passing through the resistive elements to be deposited thereon or parallel to the intended direction of. the movement of the record medium to be used with the resulting print wafer 20. As shown in FIG. 2, the grinding grooves or marks on the blended area 34 are also parallel to an imaginary plane which is mutually perpendicular to the first, second, and third faces 24,26, and 28, respectively.

The grooves of the blended area 34 (FIG. 2) provide area where the semiconductor material (to be later deposited) may lodge, so as to provide a continuity through the resulting specific resistive elements even after considerable use of the print wafer 20. This feature improves the print-to-burnout ratio of the wafer.

After the blended area 34 is formed, as shown in FIG. 2, coating of semiconductor material is applied thereto by the apparatus shown in FIG. 3. The apparatus includes a furnace 42, having therein heated blocks 44 and 46, which are brought together by a conventional clamping device 48 (shown as a block) to clamp a portion of the substrate 22 within the furnace 42. As is apparent from FIG. 3, the portion of the substrate 22 containing the blended area 34 is positioned outside the furnace 42. Suitable conventional seals (not shown) may be placed around the substrate 22 to prevent the loss of heat from the furnace 42, which is conventionally heated. Stationary spray nozzles 50 and 52, located outside the furnace 42, in the atmosphere, are used to spray semiconductor material onto the blended area 34 and portions of the first and second surfaces. The nozzles 50 and 52 may be conventional artists air brushes with plastic tips through which the semiconductor material is sprayed. The nozzles are controlled by conventional control apparatus, shown only as a block 54. Because the apparatus 54 is conventional, it is not described in detail herein. The apparatus 54 includes solenoids to control valving leading to the nozzles 50 and 52 and timing devices which control a time interval during which the nozzles spray semiconductor material onto the substrate 22 and a time interval during which the valving leading to the nozzles is closed to prevent the nozzles from spraying. Counter means are also included in the apparatus 54 to count the number of times the semiconductor material is sprayed on the substrate 22 as positioned in the furnace 42 of FIG. 3.

The semiconductor material is sprayed on the substrate 22 shown in FIG. 3 by the following technique. When tin oxide is used for the semiconductor material in one embodiment of the invention, the furnace 42 is heated to a temperature of approximately 600 Centigrade or l,350 Fahrenheit. A substrate 22 with the blended area 34 thereon is so positioned in the furnace 42, as shown in FIG. 3, that the portion containing the blended area is located outside of the furnace, and the remaining portion of the substrate is clamped between the heated blocks 44 and 46 located in the furnace. These blocks mask that portion of the substrate which does not receive the semiconductor material. The portion of the substrate located in the furnace 42 becomes heated, and, subsequently, the portion of the substrate located outside the furnace becomes heated by conduction.

The semiconductor material sprayed on the substrate 22 (FIG. 3) is in liquid form when sprayed thereon. When the semiconductor material is tin oxide, the spraying solution therefore is composed of the following ingredients:

I grams stannic trichloride 50 cc. de-ionized water i 3.5 grams antimony chloride cc. hydrochloric acid l.5 grams boric oxide The addition of boric oxide to the solution produces an improved print-to-burnout ratio for the resulting wafers 20 formed therefrom; however, the exact reason for this improvement is not known.

The spraying of the semiconductor solution (FIG. 3) is done in pulses in the following manner. With the substrate 22 heated as previously explained, both spray nozzles 50 and 52 are actuated by the control apparatus 54 to spray the semiconductor solution thereon. The nozzle 50 is directed at the first surface 24 and the third surface 28, and the nozzle 52 is directed at the second surface 26 and also at the third surface 28. Both nozzles spray the solution for about one second, and

both are then turned off for a delay interval of about 10 seconds. As a result of being sprayed, the substrate portion outside the furnace 42 becomes cooled, and the delay interval is utilized to enable that portion outside the furnace to be reheated by the remaining portion of the substrate located in the furnace. After the delay interval has elapsed, the nozzles 50 and 52 are again turned on to spray the solution on the substrate for about I second, as previously explained. The second spray interval of I second is followed by another delay interval of about lO seconds, during which the substrate portion (including the blended area 34) located outside the furnace is reheated, as previously explained. The spraying for I second followed by an interval of 10 seconds is repeated for about 25 times, at the conclusion of which, the counter means located in the control apparatus 54 indicates that the spraying operation is completed. The substrate 22, with the coating 56 (approximately 4,500 Angstroms thick) of tin oxide thereon, is then removed from the heated blocks 44 and 46 and the furnace 42, and a new substrate 22 is inserted therein. The pulsetype spraying employed and explained herein improved the print-to-burnout ratio of the wafers 20 formed thereby.

After the coating 56 of semiconductor material is sprayed on the substrate 22, it is trimmed by conventionally spraying abrasives through a mask to produce the trimmed substrate 22 shown in FIG. 4. The coating 56 is trimmed at 58 and 60 so that it extends beyond the blended area 34 on the first and second surfaces 24 and 26, respectively.

The process for dividing the coating 56 of semiconductor material (on the substrate 22) into spaced, parallel, resistive elements 62 is shown in FIG. 5. The process includes placing a slitted U-shaped, photoetched, metal mask 64 (made of a metal like brass) over the end of the substrate 22 containing the coating 56 and spraying fine abrasives at the mask 64 through a nozzle 66. The mask 64 has therein slits 68, through which the abrasives pass to separate the coating 56 into the resistive elements 62 shown. The slits 68 are about 0.002 to 0.003 inch wide, and the nozzle 66 is traversed across the width of the substrate 22 as it is moved from the first surface 24 over the blended area 34 and to the second surface 24 and back again. This process is repeated until the substrate material under the coating 56 is reached, at which time the division of the coating 56 into resistive elements 62 is effected, as shown in FIG. 6. An advantage of this method of dividing the coating 56 into resistive elements compared to prior-art methods of slitting with a diamond saw is that, in this method, the substrate material between adjacent resistive elements 62 is left to provide a heat sink therefore. In addition, the ends 70 of the resistive elements 62 may be made longer to facilitate the connection of conductor means thereto. With resistiveelement-separation by saw slitting, the depth of the cut provided by the saw is generally limited to about 0.005 to 0.008 inch. The minimum width of the saw cut is generally about 0.005 inch, whereas, with the method disclosed herein, the spacing between resistive elements, as cut by the abrasives, is generally about 0.002 to 0.003 inch. This smaller spacing provides for a wider resistive element which improves the power rating thereof and also improves the appearance of the characters formed by a print matrix using the print wafers 20 of this invention.

The conductor means which are attached to the ends 70 of the resistive elements 62 may be attached conventionally. The conductor means may include electrical conductor strips, like 72 (FIG. 7), which are attached to the ends 60 of the resistive elements 62 located on the first surface 24, and similarly, conductor strips, like 74, are attached to the ends of the resistive elements located on the second surface 26. The tips of the conductors (like 76) are best placed in the plane of the exterior of the resistive elements 62, which contacts the thermally responsive record medium, and may be positioned lower to about a distance of 0.003 inch therebelow.

Several completed print head wafers 20 in FIG. 8 are shown being assembled into a thermal print head matrix. Adjacent wafers 20 are separated by a planar dielectric member 78.

Several of the wafers 20 and dielectric members 78 are assembled together, with the resistive elements 62 lying in a common plane for cooperative association with a thermally responsive record medium (not shown). After assembly, the wafers 20 and the dielectric members 78 may be conventionally secured together by clamping or cementing to produce a completed print head matrix 80 shown in FIG.'9.

As alluded to earlier, FIGS. and 11 show the grinding apparatus 36, which is used to form the blendedarea 34 on the substrate 22 shown in FIG. 2. The grinding apparatus 36. includes a lap-flat surface 82 on a disc 84, which is rotatably supportedin bearings 86 and 88 fixed in a frame 90; The disc 84 is rotated by a motor 92 and has a layer of abrasive paper 94 approximately 0.003 inch thick secured to its lap-flat surface 82. A substrate 22 which is to be machined thereby is detachably secured against a vertical wall 96- of a rotatable member 98, so that the third surface 28 of the substrate 22 touches the abrasive paper 94. The rotatable member 98 has a plurality of passages 100 therein (only one shown in FIG. 10), which communicate with associated openings (not shown) in the wall 96 and connect the openings to associated flexible hoses 102 (only one shown in FIG. 10), which are connected to a conventional sourceof vacuum 104, which can be turned on and off as desired. By this arrangement, a wafer 22 may be detachably held against the wall 96.

The wall 96 of the rotatable member 98 is positioned perpendicular to the surface 82 of the disc 84 in one limit position, shown in FIG. 9, and is rotatablethrough an angle of 90 degrees, represented by the are 106, to a second limit position, in which the wall 96 is parallel to the surface 82 of the disc-84. To effect this rotation, the rotatable member 98 is rotated'on a flanged circular plate 108, which is secured to the frame 90 by fasteners 100. The rotatable member 98 hasahandle ll2extending therefrom to rotate the member and the wafer 22, secured thereto, through an angle of 90 between the limit stops mentioned. The rotatable member 98 is so positioned, relative to theframe 90, that the center of a wafer- 22' (when secured to the wall 96) will lie along a radial line relative to the disc 84. The rotatable member 98 is displaced from the center of the disc 84 toward its perimeter, as shown in FIG. 10. When a wafer 22 is secured to the wall. 96 and-the rotatable member 98 is rotated through 90, one of the first or second common edges is removed. The rotatable member 98 is then rotated back to the position shown in FIG. 10; and the wafer 22 is released from the wall 96, reversed, and secured thereto to repeat the process for removing the remaining common edge. By this technique, the blended area 34 shown in FIG. 2 is obtained. The radii 38 and 40 (FIG. 2) produced by this apparatus are more accurate than can be made manually. These radii prolong the life of the resulting wafer FIG. 8) because the record medium, when brought into engagement therewith, does not have a tendency to abrade the resistive elements 62 to cause discontinuity therein. With no radii on the edges 30 and 32, the record medium would-abrade against these edges of the resistive elements and cause discontinuity therein, thereby shortening the useful life of the print head wafer.

Iclaim:

l. A thermal print wafer comprising:

a dielectric substrate having first and second opposed planar surfaces, mutually, substantially perpendicular to a third surface thereof;

said first, second, and third surfaces being formed to provide one continuous blended area extending completely over said third surface and partly over said first and second surfaces;

said blended area having small grooves therein below the surface thereof; said grooves being aligned substantially parallel to an imaginary plane mutually perpendicular to said first, second, and third surfaces; and

a plurality of discrete resistive elements secured'to said blended area and extending completely across said third surface and partly over said first and second surfaces;

said resistive elements being positioned in spaced parallel relationship with one another and having portions filling said grooves. 2. The wafer as claimed in claim 1 in which said substrate has a constant radius of curvature joining said first and third surfaces a'ndanother constant radius of curvature joining said second and third surfaces at said blended area.

3. The wafer as claimed in claim 2 in which said substrate is continuous at said blended area so as to form a heat sink for said resistive elements.

4. The wafer as claimed in claim 1 in which said resistive elements aremade of semiconductor material.

5. The wafer as claimed in claim 4 in which said semiconductor material is tin oxide which has a small'amount of boric oxide therein to increase the print-to-burnout ratio of the resistive elements.

6. The wafer as claimed in claim 1 in which said resistive elements are spaced apart a short distance when compared to the width of individual resistive elements so as to increase the print-to-burnout ratio of the resistive elements.

The wafer as claimed in claim 1 further comprising: electrical conductor means for energizing selected onesof said resistive elements; said conductor means being located on said. first andsecond surfaces of said substrate. 8; A thermal print head comprising: a plurality of printwafers and insulating members alternately arranged in a stacked array with one of said insulating members being positioned between two adjacent-print wafers; eachsaid print wafer comprising: a dielectric substrate having first and second opposed planar surfaces mutually, substantially perpendicular to a third surfacethereof; said first, second, and third surfaces being formed to provide one continuous blended area extending completely over said third surface and partly over said first and second surfaces; said blended area having small grooves therein below the surface thereof; said grooves being aligned substantially parallel to an imaginary plane mutually perpendicular to said first, second, and third surfaces;

a plurality of discrete resistive elements secured to said blended area and extending completely acrossv saidthird surface and partly over said first and second sur faces; i

said resistive elements being positioned in spaced parallel relationship with one another and having portions filling said grooves; and

electrical conductor means for energizing selected ones of said resistive elements;

said conductor means being located on said' first and secondsurfaces of each said substrate;

said thirdsurfaces of said substrates lying substantially in a common plane so thatv the resistive elements positioned thereon cancooperate with a thermally sensitive record medium to produce a mark on said recordmedium when a selected resistive element is energized.

9. A thermal print wafer for thermally marking a thermally responsive record medium which moves in a predetermined direction past said printing wafer comprising:

a dielectric substrate having first and second opposed planar surfaces mutually perpendicular to a third surface thereof;

said first, second, and third surfaces being formed toprovide one. continuous blended area extending completely over said third surface and partly over said first and second surfaces;

said blended area having small grooves therein below the surface thereof with the grooves being aligned substantially parallel to said predetermined direction;

a plurality of discrete resistive. elements secured to said blended area and'extending completely across said'third.

surface and partly over said first and second surfaces;

said resistive elements being positioned in spaced parallel relationship with one another and having portions filling said grooves; and

electrical conductor means positioned on said first and second surfaces for energizing selected ones of said resistive elements.

10. A method of forming a plurality of resistive elements along an edge of a dielectric substrate comprising the steps of:

a. providing a dielectric substrate having first and second planar surfaces substantially mutually perpendicular to a third surface thereof so as to provide a first common edge between said first and third surfaces and a second common edge between said second and third surfaces;

b. forming a portion of said first and second surfaces and said third surface into one continuous blended area by forming precise radii at said first and second common edges, and by forming small grooves lying below the surface of said blended area;

c. applying semiconductor material over a portion of said substrate including said blended area; and

d. dividing said semiconductor material into discrete resistor elements.

11. The method as claimed in claim 10 in which said step (b) forming is accomplished by grinding in the direction of anticipated current flow through the resistor elements to be formed.

12. The method as claimed in claim 11 in which said step (c) applying semiconductor material is accomplished while exposing said portion of said substrate including the blended area to the atmosphere while heating the remaining portion thereof;

13. The method as claimed in claim 12 in which said step (c) applying semiconductor material is accomplished by spraying said semiconductor material in liquid form through at least one nozzle located in the atmosphere and directed at said portion which is exposed to the atmosphere.

14. The method as claimed in claim 13 in which said step (c) applying semiconductor material is effected by spraying in time-spaced pulses with the time between pulses enabling the portion of the substrate exposed to the atmosphere to be reheated by the remaining portion thereof which is heated continuously.

15. The method as claimed in claim 14 in which the heating of the remaining portion of the substrate is effected by locating the remaining portion of the substrate in a furnace, a portion of the furnace being used for masking the remaining portion of the substrate which does not receive the semiconductor material.

16. The method as claimed in claim 10 in which said step (d) dividing said semiconductor material into discrete resistor elements is effected by covering said semiconductor material with a slitted U-shaped mask and by spraying abrasive material through the slits in the mask at said semiconductor material.

17. The method as claimed in claim 10 in which said step (b) forming said first, second, and third surfaces into one continuous blended area comprises:

positioning said substrate so that the first and third planar surfaces thereof are perpendicular to a moving planar abrasive surface so that said third surface contacts said abrasive surface;

rotating said substrate through an angle of 90 degrees so as to form a precise radius on said first edge;

repositioning said substrate so that said first and third planar surfaces thereof are perpendicular to said planar abrasive surface so that said third surface contacts said moving abrasive surface; and

rotating said substrate through an angle of 90 so as to form a precise radius on said second edge. 

1. A thermal print wafer comprising: a dielectric substrate having first and second opposed planar surfaces, mutually, substantially perpendicular to a third surface thereof; said first, second, and third surfaces being formed to provide one continuous blended area extending completely over said third surface and partly over said first and second surfaces; said blended area having small grooves therein below the surface thereof; said grooves being aligned substantially parallel to an imaginary plane mutually perpendicular to said first, second, and third surfaces; and a plurality of discrete resistive elements secured to said blended area and extending completely across said third surface and partly over said first and second surfaces; said resistive elements being positioned in spaced parallel relationship with one another and having portions filling said grooves.
 2. The wafer as claimed in claim 1 in which said substrate has a constant radius of curvature joining said first and third surfaces and another constant radius of curvature joining said second and third surfaces at said blended area.
 3. The wafer as claimed in claim 2 in which said substrate is continuous at said blended area so as to form a heat sink for said resistive elements.
 4. The wafer as claimed in claim 1 in which said resistive elements are made of semiconductor material.
 5. The wafer as claimed in claim 4 in which said semiconductor material is tin oxide which has a small amount of boric oxide therein to increase the print-to-burnout ratio of the resistive elements.
 6. The wafer as claimed in claim 1 in which said resistive elements are spaced apart a short distance when compared to the width of individual resistive elements so as to increase the print-to-burnout ratio of the resistive elements.
 7. The wafer as claimed in claim 1 further comprising: electrical conductor means for energizing selected ones of said resistive elements; said conductor means being located on said first and second surfaces of said substrate.
 8. A thermal print head comprising: a plurality of print wafers and insulating members alternately arranged in a stacked array with one of said insulating members being positioned between two adjacent print wafers; each said print wafer comprising: a dielectric substrate having first and second opPosed planar surfaces mutually, substantially perpendicular to a third surface thereof; said first, second, and third surfaces being formed to provide one continuous blended area extending completely over said third surface and partly over said first and second surfaces; said blended area having small grooves therein below the surface thereof; said grooves being aligned substantially parallel to an imaginary plane mutually perpendicular to said first, second, and third surfaces; a plurality of discrete resistive elements secured to said blended area and extending completely across said third surface and partly over said first and second surfaces; said resistive elements being positioned in spaced parallel relationship with one another and having portions filling said grooves; and electrical conductor means for energizing selected ones of said resistive elements; said conductor means being located on said first and second surfaces of each said substrate; said third surfaces of said substrates lying substantially in a common plane so that the resistive elements positioned thereon can cooperate with a thermally sensitive record medium to produce a mark on said record medium when a selected resistive element is energized.
 9. A thermal print wafer for thermally marking a thermally responsive record medium which moves in a predetermined direction past said printing wafer comprising: a dielectric substrate having first and second opposed planar surfaces mutually perpendicular to a third surface thereof; said first, second, and third surfaces being formed to provide one continuous blended area extending completely over said third surface and partly over said first and second surfaces; said blended area having small grooves therein below the surface thereof with the grooves being aligned substantially parallel to said predetermined direction; a plurality of discrete resistive elements secured to said blended area and extending completely across said third surface and partly over said first and second surfaces; said resistive elements being positioned in spaced parallel relationship with one another and having portions filling said grooves; and electrical conductor means positioned on said first and second surfaces for energizing selected ones of said resistive elements.
 10. A method of forming a plurality of resistive elements along an edge of a dielectric substrate comprising the steps of: a. providing a dielectric substrate having first and second planar surfaces substantially mutually perpendicular to a third surface thereof so as to provide a first common edge between said first and third surfaces, and a second common edge between said second and third surfaces; b. forming a portion of said first and second surfaces and said third surface into one continuous blended area by forming precise radii at said first and second common edges, and by forming small grooves lying below the surface of said blended area; c. applying semiconductor material over a portion of said substrate including said blended area; and d. dividing said semiconductor material into discrete resistor elements.
 11. The method as claimed in claim 10 in which said step (b) forming is accomplished by grinding in the direction of anticipated current flow through the resistor elements to be formed.
 12. The method as claimed in claim 11 in which said step (c) applying semiconductor material is accomplished while exposing said portion of said substrate including the blended area to the atmosphere while heating the remaining portion thereof.
 13. The method as claimed in claim 12 in which said step (c) applying semiconductor material is accomplished by spraying said semiconductor material in liquid form through at least one nozzle located in the atmosphere and directed at said portion which is exposed to the atmosphere.
 14. The method as claimed in claim 13 in which said step (c) applying semiconductor material is effected by spraying in time-spaced pulses with the time between pulses enabling the portion of the substrate exposed to the atmosphere to be reheated by the remaining portion thereof which is heated continuously.
 15. The method as claimed in claim 14 in which the heating of the remaining portion of the substrate is effected by locating the remaining portion of the substrate in a furnace, a portion of the furnace being used for masking the remaining portion of the substrate which does not receive the semiconductor material.
 16. The method as claimed in claim 10 in which said step (d) dividing said semiconductor material into discrete resistor elements is effected by covering said semiconductor material with a slitted U-shaped mask and by spraying abrasive material through the slits in the mask at said semiconductor material.
 17. The method as claimed in claim 10 in which said step (b) forming said first, second, and third surfaces into one continuous blended area comprises: positioning said substrate so that the first and third planar surfaces thereof are perpendicular to a moving planar abrasive surface so that said third surface contacts said abrasive surface; rotating said substrate through an angle of 90* degrees so as to form a precise radius on said first edge; repositioning said substrate so that said first and third planar surfaces thereof are perpendicular to said planar abrasive surface so that said third surface contacts said moving abrasive surface; and rotating said substrate through an angle of 90* so as to form a precise radius on said second edge. 